Alif Semiconductor /AE302F80F5582AE_CM55_HP_View /M55HE_CFG /HE_CLK_ENA

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HE_CLK_ENA

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)NPU_CKEN 0 (Val_0x0)DMA_CKEN 0 (Val_0x0)PDM_CKEN 0 (Val_0x0)PDM_CKSEL 0 (Val_0x0)CPI_CKEN 0 (Val_0x0)SPI_CKEN

PDM_CKEN=Val_0x0, SPI_CKEN=Val_0x0, PDM_CKSEL=Val_0x0, CPI_CKEN=Val_0x0, NPU_CKEN=Val_0x0, DMA_CKEN=Val_0x0

Description

Peripheral Clock Enable Register

Fields

NPU_CKEN

Enable clock for NPU-HE

0 (Val_0x0): Disable clock

1 (Val_0x1): Enable clock

DMA_CKEN

Enable clock for DMA2 and EVTRTR2

0 (Val_0x0): Disable clock

1 (Val_0x1): Enable clock

PDM_CKEN

Enable clock for LPPDM

0 (Val_0x0): Disable clock

1 (Val_0x1): Enable clock

PDM_CKSEL

Select clock source for LPPDM

0 (Val_0x0): Select 76.8 MHz crystal-oscillator clock (76M8_CLK)

1 (Val_0x1): Select external audio clock input (AUDIO_CLK)

CPI_CKEN

Enable clock for LPCPI

0 (Val_0x0): Disable clock

1 (Val_0x1): Enable clock

SPI_CKEN

Enable clock for LPSPI

0 (Val_0x0): Disable clock

1 (Val_0x1): Enable clock

Links

() ()